1. Field of Use
The present invention relates to arithmetic processing apparatus and more particularly to apparatus for detecting the presence of invalid operands.
2. Prior Art
During the process of executing certain types of arithmetic operations, such as shift left operations, it is possible that the operand being shifted may become invalid. To maintain system integrity, it becomes necessary to be able to detect and identify this event as an overflow condition. This is normally done by detecting that the resultant operand lost significant bits and then setting an overflow indicator register.
In one prior art system, the overflow condition was detected by checking the validity of the sign bit and operand after each cycle of the shifting operation. It was found that this process was very time consuming and required a substantial amount of logic circuits. Accordingly, when this type of arrangement is implemented in macrocell array form, it is too slow and requires a considerable amount of chip area.
Accordingly, it is a primary object of the present invention to provide an arrangement for detecting overflow conditions within a minimum amount of time.
It is a further object of the present invention to provide a scheme which requires a small amount of circuits so as to be readily implementable in macrocell array form.